1. Field of the Invention
The present invention relates to a multiprocessor system including a plurality of processors.
2. Description of the Background Art
Various techniques have been proposed from the related art regarding the multiprocessor system including a plurality of processors. For instance, a technique of distributing the load of an interrupt processing in a bus-sharing multiprocessor system to enhance system performance is disclosed in Japanese Patent Application Laid-Open No. 5-324569. A technique related to interrupt processing in the multiprocessor system is also disclosed in Japanese Patent Application Laid-Open No. 8-36498, Japanese Patent Application Laid-Open No. 9-212472, Japanese Patent Application Laid-Open No. 2001-236238, and Japanese Patent Application Laid-Open No. 2005-182177.
A technique in which a plurality of interrupt causes shares one interrupt request, in other words, a technique in which a signal line for transmitting the interrupt request is shared among a plurality of devices at where the interrupt cause occurs is used in a multiprocessor system having a PCI (Peripheral Components Interconnect) bus, and the like.
In the conventional multiprocessor system, a plurality of interrupt requests can be assigned to different processors, but the plurality of interrupt causes can only be processed in one processor if the plurality of interrupt causes is sharing one interrupt request. Therefore, the interrupt request must be assigned individually to each of the plurality of interrupt causes in order to process the plurality of interrupt causes in different processors. As a result, the types of interrupt requests increase, and the number of signal lines for transmitting the interrupt request increases.